New Embedded System I/O Expansion Standard
A new embedded system I/O expansion standard, originated by Diamond Systems, will be launched at Embedded World 2010 in Nuremberg, Germany on March 2, 2010. The new mezzanine-style standard defines a highly compact, low cost way to add application-oriented capabilities to single-board computers (SBCs), computer-on-module (COM) baseboards, and fully-custom embedded electronics. The new I/O expansion standard enable engineers to add application-specific capabilities to SBCs and COM baseboards without adding height to the system.
Breaking the Flat File Barrier for Embedded Developers White Paper
ITTIA published a white paper about the challenges of hard-coded data management. The white paper explores the use of custom binary and text file formats, and shows how they are inadequate for applications that are better served by a more suitable lightweight relational database solution. The technical paper is titled, Breaking the Flat File Barrier for Embedded Developers.
Fundamentals of Embedded Test Webinar
Tektronix is offering an On Demand webinar about the Fundamentals of Embedded Test. The 40-minute, comprehensive webcast will offer insight on what to look for, where the 'gotchas' lie, and how and where signal interaction and crosstalk can throw the system off. The online seminar will cover the basics of testing embedding systems. It is presented by John Ziegler, Director of Engineering, octoScope.
Texas Instruments DesignStellaris 2010 Design Contest
Texas Instruments announced the DesignStellaris 2010 design contest for embedded engineers. Each entry will be judged equally on technical merit, originality, usefulness, cost-effectiveness and design optimization by an independent panel of judges. Additional points will be awarded for the use of the StellarisWare IEC60730 library and for applications that improve safety or reliability with SafeRTOS. DesignStellaris 2010 contest will take place through June 23, 2010.
AVIX RTOS v3.5 Features Integrated Energy Reduction Functionality
AVIX-RT announced version 3.5 of its AVIX RTOS. Building on the capabilities of its predecessor, this new version offers functionality to exploit the energy saving capabilities of the applied microcontroller. Especially beneficial for battery powered devices applying this new version of the AVIX RTOS can result in a substantial decrease in energy consumption.
Synopsys Gains Virtual Prototyping Solutions by Acquiring VaST Systems
Synopsys, Inc. (Nasdaq: SNPS), a world leader in software and IP for semiconductor design, verification and manufacturing, announced it has acquired VaST Systems Technology Corporation to extend its virtual prototyping solutions into the automotive and consumer application space. The acquisition adds a comprehensive set of processor sub-system models frequently found in automotive and consumer applications to Synopsys' virtual prototyping portfolio. Processor sub-system models allow developers to accelerate the virtualization of electronic systems and to start software development nine to 12 months prior to the availability of silicon.
High Bandwidth System Design Implementations with FPGA Webinar
Xilinx has a webinar titled, Accelerating High-Bandwidth System Design Implementations with FPGA-based platforms. The webcast will explain how the Targeted Reference Design, delivered through the Xilinx Connectivity Kits, jumpstarts application development by providing a complete design flow for an end-to-end system application — hardware design and RTL source files, simulation environment, implementation flows and scripts, software device driver source files, performance/status monitor application, and documentation.
Altera 28nm FPGAs
Altera's upcoming 28nm FPGAs will feature Embedded HardCopy Blocks, 28-Gbps embedded transceivers, and user-friendly partial reconfiguration. Embedded HardCopy Blocks will improve the density and I/O performance of next-generation Altera FPGAs. High-speed transceivers will help designers implement designs such as 400G systems on a single chip without the need for costly external components. Partial reconfiguration enables designers to reconfigure part of the FPGA while other sections remain running.
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